The present invention relates to a semiconductor device and a method of fabricating the device, and more particularly to a semiconductor device including a field-effect transistor and a method of fabricating the device.
Among high voltage transistors, a structure called a LOCOS offset type is known which includes a thick field oxide film (thereinafter referred to as LOCOS) at an end of a gate electrode or between the gate electrode and a drain diffusion layer and between the gate electrode and a source diffusion layer.
Japanese Patent Laid-Open No. 2001-94103 discloses a high voltage transistor structure. In this structure, an offset diffusion layer in the source side has the same concentration and depth as an offset diffusion layer in the drain side, but the size of the offset diffusion layer is set greater in the source side than in the drain side. More specifically, when the size of the offset diffusion layer in the drain side is Ld and the size of the offset diffusion layer in the source side is Ls, Ld is set smaller than Ls. Accordingly, the resistance of the offset diffusion layer in the source side becomes greater and thus the source voltage VS becomes higher. Consequently, when the substrate voltage is VW, VW minus the forward junction breakdown voltage of silicon can be readily kept equal or smaller than VS and the sustaining breakdown voltage becomes higher.
However, the present inventor has noticed that, since the size Ld of the offset diffusion layer in the drain side is smaller than the size Ls of the offset diffusion layer in the source side according to the technique described in Japanese Patent Laid-Open No. 2001-94103, the gate-source distance becomes longer and thus the On-resistance becomes higher. Further, since the size of the offset diffusion layer in the drain side is small, the Off-breakdown voltage becomes lower.